1. Field of the Invention
The present invention relates to an image display device, and more particularly to a gate driving apparatus to prevent a deterioration of picture quality caused by a gate flickering phenomenon, and an image display device using the gate driving apparatus and a driving method thereof.
2. Discussion of the Related Art
With development in the information society, demands for various display devices have increased. Accordingly, significant efforts have been made to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some species of the flat display devices are already applied to displays of various equipments.
FIG. 1 is a block diagram of schematically illustrating a related art LCD device. As shown in FIG. 1, the related art LCD device is provided with an LCD panel 10 which includes a plurality of gate lines (GL1 to GLn) and data lines (DL1 to DLm) formed perpendicularly. The data driver 20 supplies video signals to the data lines (DL1 to DLm), the gate driver 30 supplies scan pulses to the gate lines (GL1 to GLn), and the timing controller 40 controls the driving timing of the data and gate drivers 20 and 30.
The LCD panel 10 includes a plurality of thin film transistors (TFTs) formed in portions defined by n gate lines (GL1 to GLn) and m data lines (DL1 to DLm). A plurality of liquid crystal cells are connected with the thin film transistors (TFTs). Each thin film transistor (TFT) supplies the video signal provided from the data lines (DL1 to DLm) to the liquid crystal cell in response to the scan pulse provided from the gate lines (GL1 to GLn). The liquid crystal cell is provided with a common electrode and a pixel electrode being connected with the thin film transistor (TFT). The liquid crystal layer is disposed between the common electrode and the pixel electrode. Thus, the liquid crystal cell may be equivalently represented as a liquid crystal capacitor (Clc). In addition, the liquid crystal cell includes a storage capacitor (Cst) that maintains the data voltage charged in the liquid crystal capacitor (Clc) until the next data signal is charged.
The timing controller 40 arranges the source data (RGB) that is provided from the external source to be appropriate for the driving of the LCD panel 10. Thereafter, the timing controller 40 supplies the arranged source data to the data driver 20. In addition, the timing controller 40 generates control signals (DCS, GCS) to control the data driver 20 and the gate driver 30 by using synchronization signals (DE, DCLK, Hsync, Vsync) provided from the external source.
The data driver 20 converts the data (Data) provided from the timing controller 40 to an analog video signal in accordance with the data control signal (DCS) provided from the timing controller 40. Thereafter, the data driver 20 supplies the analog video signal to the data lines (DL1 to DLm) for one horizontal line by one horizontal period to supply the scan pulse to each gate line (GL1 to GLn). In particular, the data driver 20 selects one gamma voltage corresponding to the data (Data) from a plurality of gamma voltages, takes the selected gamma voltage as the analog video signal, and supplies the selected gamma voltage to the data lines (DL1 to DLm).
The gate driver 30 generates the scan pulse, that is, high gate pulse in accordance with the gate control signal (GCS) provided from the timing controller 40, and sequentially supplies the generated scan pulse to the gate lines (GL1 to GLn). In response to the scan pulses, the thin film transistor (TFT) is turned-on, whereby the video signal of the data line (DL1 to DLm) is supplied to the capacitors (Clc) of the corresponding liquid crystal cells.
FIG. 2 is a circuit diagram illustrating the gate driver shown in FIG. 1 according to the related art. As shown in FIG. 2, the related art gate driver 30 is provided with a shift register 32, a logic-operation unit 36, a level-shift unit 38, and a buffering unit 39.
The shift register 32 sequentially generates a shift signal by using a gate start pulse (GSP) and a gate shift clock (GSC). In particular, the shift register 32 includes n-th flip-flops which sequentially shift the gate start pulse (GSP) in accordance with the gate shift clock (GSC).
The logic-operation unit 36 performs a logic operation for the shift signal provided from the shift register 32 and a gate output enable signal (GOE), and supplies the result to the level-shift unit 38. In particular, the logic operation unit 36 includes an inverter 34 which inverts and outputs the gate output enable signal (GOE), and the AND-gates which are connected with respective output terminals of the flip-flops of the shift register 32 and an output terminal of the inverter 34. The AND-gates supply an output signal of a high state to the level-shift unit 38 when the inverted gate output enable signal (GOE) and the shift signal provided from the flip-flop are both in the high state. If either signal is in the low state, the AND-gates supply an output signal of a low state to the level-shift unit 38.
The level-shift unit 38 includes n level shifters, each connected with each output terminal of the AND-gates. The level shifters shift the output signal provided from each AND-gate to the level suitable for the driving of liquid crystal cell, and supplies the shifted signal to the buffering unit 39.
The buffering unit 39 includes n buffers, each connected with each output terminal of the level shifters. The buffers buffer the output signal provided from each level shifter corresponding to the load of gate lines (GL1 to GLn), and supply the buffered signal to the gate lines (GL1 to GLn).
As shown in FIG. 3, the gate driver 30 according to the related art sequentially shifts the gate start pulse (GSP) in accordance with the gate shift clock (GSC). Furthermore, the gate driver 30 generates a level shift signal in accordance with the gate output enable signal (GOE), and sequentially supplies the level shifted signal to the gate lines (GL1 to GLn). The related art LCD device sequentially supplies the scan pulse to the gate lines (GL1 to GLn) of the LCD panel 10 by using the gate driver 30. At the same time, the LCD device supplies the video signal to the data lines (DL1 to DLm) in synchronization with the scan pulse, to thereby display the desired image.
However, as shown in FIG. 4, if the gate start pulse (GSP) is distorted due to the electric shock or noise, the scan pulse supplied to the LCD panel 10 can be provided non-sequentially, or even partially-overlapped, thereby generating a gate flickering phenomenon wherein images are shifted or overlapped. Accordingly, the picture quality is deteriorated due to a gate flickering phenomenon generated by the electric shock or noise.